The present invention relates to an output circuit, a data driver using it, and a display device.
Currently, among display devices, the liquid crystal display device (LCD) that features a thin form, a light weight, and low power consumption spreads broadly, and find its uses not only in the laptop PC and the monitor, but also in the large screen liquid crystal television, the multifunctional cellular phone, the tablet type highly sophisticated information terminal, etc. As these liquid crystal display devices, many liquid crystal display devices of the active matrix drive system each of which can perform a high definition display are used. Moreover, as a thin display device which ranks second to the liquid crystal display device, development of a display device of the active matrix drive system using an organic light-emitting diode (OLED) that features light-emitting by itself and a clear image quality is also being advanced.
With reference to FIG. 12, a typical configuration of the thin display device of the active matrix drive system (the liquid crystal display device and an organic light-emitting diode display device) will be outlined. Incidentally, FIG. 12A shows a principal part configuration of the thin display device by a block diagram, FIG. 12B shows a principal part configuration of a unit pixel of a display panel of the liquid crystal display device, and FIG. 12C shows a principal part configuration of a display panel of the organic light-emitting diode display device, respectively. The unit pixels of FIG. 12B and FIG. 12C are represented by schematic equivalent circuits, respectively.
Referring to FIG. 12A, generally, the thin display device of the active matrix drive system is comprised of a power supply circuit 940, a display controller 950, a display panel 960, a gate driver 970, and a data driver 980. In the display panel 960, the unit pixels each containing a pixel switch 964 and a display element 963 are arranged in a matrix form (for example, in the case of a color SXGA (Super eXtended Graphics Array) panel, 1280×3 pixel column×1024 pixel row), and a scanning line 961 for sending a scanning signal outputted to each unit pixel from the gate driver 970 and a data line 962 for sending a gradation voltage signal outputted from the data driver 980 are wired in a grid form. Incidentally, the display controller 950 controls the gate driver 970 and the data driver 980, respectively, and supplies clock CLK, control signal, etc. that are required respectively, and image data is supplied to the data driver 980 in a digital signal. The power supply circuit 940 supplies electrical power necessary for the gate driver 970 and the data driver 980. The display panel 960 is comprised of a semiconductor substrate, and especially in a large screen display device, a semiconductor substrate such that pixel switches etc. are formed with thin film transistors (TFTs) over an insulating substrate, such as a glass substrate and a plastic substrate, is widely used.
The above-mentioned display devices controls on/off of the pixel switch 964 by a scanning signal, and when the pixel switch 964 is turned on, it displays an image by applying the gradation voltage signal corresponding to the image data to the display element 963 to effect variation in brightness of the display element 963 according to the gradation voltage signal.
Rewriting of the data for one screen is performed every one frame period (usually about 0.017 sec at the time of 60-Hz driving), selection (the pixel switch is turned on) is performed sequentially for every one pixel line (each line) by each scanning line 961, and each data line 962 supplies the gradation voltage signal to the display element 963 through the pixel switch 964 in a selection period. Incidentally, there are cases where multiple pixel lines with corresponding multiple lines are selected simultaneously or where the scanning line is driven at 120 Hz or at a higher frame frequency in order to improve a motion picture characteristic.
In the case of the liquid crystal display device, referring to FIG. 12A and FIG. 12B, the display panel 960 is comprised of a structure of a semiconductor substrate over which the pixel switches 964 and transparent pixel electrodes 973, as the unit pixels, are arranged in a matrix form, an opposing substrate over the whole plane of which a single transparent electrode 974 is formed, and liquid crystal enclosed between these two substrates being opposed. Incidentally, the display element 963 forming the unit pixel has a pixel electrode 973, an opposing substrate electrode 974, a liquid crystal capacitance 971, and an auxiliary capacitance 972. Moreover, it has a backlight over the back of the display panel as a luminous source.
When the pixel switch 964 is turned on (conduction) by the scanning signal from the scanning line 961, the gradation voltage signal from the data line 962 is applied to the pixel electrode 973, the transmissivity of the light from the backlight penetrating the liquid crystal varies by the potential difference between each pixel electrode 973 and the opposing substrate electrode 974, and even after the pixel switch 964 is turned off (non-conduction), the potential difference is maintained for a fixed period by the liquid crystal capacitance 971 and the auxiliary capacitance 972, whereby display is performed.
Incidentally, in driving of the liquid crystal display device, in order to prevent degradation of the liquid crystal, a drive (inversion driving) whereby voltage polarity (positive or negative) of the pixel electrode 973 is switched to the common voltage of the opposing substrate electrode 974, usually with one frame period, is performed. As typical examples, there are dot inversion driving where the voltage has a different voltage polarity between adjacent pixels and column inversion driving where the voltage has a different voltage polarity between adjacent pixel columns. In the dot inversion driving, the gradation voltage signal of a different voltage polarity is outputted to one data line for each selection period (one data period); in the column inversion driving, the gradation voltage signal is outputted with the same voltage polarity in each selection period (data period) in the one frame period but with a different voltage polarity in each frame period.
In the case of the organic light-emitting diode display device, referring to FIG. 12A and FIG. 12C, the display panel 960 is comprised of a semiconductor substrate over which the pixel switch 964, an organic light-emitting diode 982 made of an organic film sandwiched by two thin-film electrode layers and thin film transistors (TFTs) 981 each for controlling a current supplied to the organic light-emitting diode 982 (these two members serving as the unit pixel), are arranged in a matrix form. The TFT 981 and the organic light-emitting diode 982 are coupled together in series between the power supply terminal 984 and the power supply terminal 985 (cathode electrode) to which different power supply voltages are supplied, and further have an auxiliary capacitance 983 for maintaining a control terminal voltage of the TFT 981. Incidentally, the display element 963 corresponding to one pixel is comprised of the TFT 981, the organic light-emitting diode 982, power supply terminals 984, 985, and the auxiliary capacitance 983.
Display is performed as follows: when the pixel switch 964 turns on (conduction) by the scanning signal from the scanning line 961, the gradation voltage signal from the data line 962 is applied to a control terminal of the TFT 981; a current corresponding to the gradation voltage signal is supplied to the organic light-emitting diode 982 by the TFT 981; and the organic light-emitting diode 982 emits light at a brightness according to the current. Even after the pixel switch 964 is turned off (non-conduction), light emission is held by maintaining the gradation voltage signal applied to the control terminal of the TFT 981 for a fixed period with the auxiliary capacitance 983. Incidentally, although the pixel switch 964 and the TFT 981 show an example of n-channel type transistors, it is also possible for them to be comprised of p-channel type transistors. Moreover, a configuration in which the organic light-emitting diode is coupled to a power supply terminal 984 is also possible. Moreover, in driving of the organic light-emitting diode display device, inversion driving like in the liquid crystal display device is not necessary, and the gradation voltage signal corresponding to the pixel is outputted to the data line 962 at every selection period (one data period).
Incidentally, although the organic light-emitting diode display device also has a configuration in which display is performed by receiving a gradation current signal outputted from the data driver, aside from the above-explained configuration in which display is performed by receiving the gradation voltage signal from the data line 962, an explanation in this description will be given limiting to the configuration in which display is performed by receiving the gradation voltage signal outputted from the data driver.
In FIG. 12A, while the gate driver 970 must just supply the scanning signal of at least binary, the data driver 980 is required to drive each data line 962 with the gradation voltage signal of multi-valued levels according to the number of gradation. Consequently, the data driver 980 has an output circuit for amplifying and outputting the gradation voltage signal corresponding to the image data to the data line 962.
In high-end use mobile apparatuses, laptop PCs, monitors, televisions, etc each of which has a thin display device, a demand for higher definition is being sought. Specifically, the following requests have started to be placed: a request of multi-color rendering (higher gradation) more than or equal to 8-bit image data for each color of RGB (about 16,800,000 colors); and a request of increasing the frame frequency (driving frequency at which one screen is rewritten) to 120 Hz or more higher than this in order to improve a motion picture characteristic and to support three-dimensional representation. If the frame frequency becomes N times larger, one data output period will be about 1/N times smaller.
The data driver of the display device has become asked to perform high-speed driving of the data line together with a high-precision voltage output that corresponds to increased gray scales. Therefore, in order to charge and discharge the data line capacitance at high speed, an output circuit of the data driver 980 is required to have a high driving capability. Moreover, in order to attain uniformity in writing of the gradation voltage signal to the display element, symmetry of a slew rate of a data line driving waveform at the time of charging and discharging is also required. However, the output circuit has an increased consumption current with its higher driving capability. Consequently, problems of an increase in power consumption and generation of heat are newly brought forward.
Next, with reference to FIG. 11, an output range of the data driver for display will be explained. Incidentally, FIG. 11 is a drawing created by the inventors of this application in order to explain problems of a pertinent art. FIG. 11A shows the output range of an LCD driver. VDD and VSS denote a high-level power supply voltage and a low-level power supply voltage, respectively (generally VSS is a ground potential=0 V). The LCD driver performs a polarity inversion driving of a positive voltage (high potential side) and a negative voltage (low potential side) to a common voltage COM of an opposing substrate electrode that is near the medium of the power supply voltages VDD and VSS.
FIG. 11B shows an output range of the OLED driver of active matrix drive (of voltage program type). The OLED driver has no polarity inversion drive as in the LCD. FIG. 11B shows an example in which the output range is (VSS+Vdif) to VDD. A voltage difference Vdif is governed by a potential difference between electrodes required for an OLED element formed over the display panel to emit light and a threshold voltage of a transistor over the display panel for controlling a current supplied to the OLED element.
One example of the pertinent art of driving the data line of the display device at high speed will be explained below. FIG. 13 is a diagram cited from FIG. 3 of 6.6L: Late-News Paper: A Low Quiescent Current and Fast Settling Output Buffer with Boosting Slew-rate Scheme for Large LCD driver, II Kwon Chang et al., SID 10 DIGEST, pp. 74-76, 2010. FIG. 13 discloses an output buffer that boosts the slew rate to aim at shortening of a settling time and attaining lower power consumption as an output buffer of the data driver for display (a large-sized LCD driver). In FIG. 13, the output buffer is formed by having a differential amplifier 700 (excluding an SBC 710) and the slew rate boost circuit (SBC: Slew Boosting Circuit) 710 for boosting the slew rate according to a difference between an input voltage and an output voltage. Incidentally, the differential amplifier 700 of FIG. 13 has a configuration based on Japanese Unexamined Patent Publication No. Hei6 (1994)-326529.
Referring to FIG. 13, the differential amplifier 700 has: a current source IN1 whose one end is coupled to a low potential side power supply terminal (a GND terminal); Nch transistors N1, N2 whose sources are coupled in common to the other end of the current source IN1, whose gates are coupled to an input terminal INP and an output terminal OUT, respectively, and that form an Nch differential pair; a current source IP1 whose one end is coupled to a high potential side power supply terminal (power supply terminal); Pch transistors P1, P2 whose sources are coupled in common to the other end of the current source IP1, whose gates are coupled to the input terminal INP and the output terminal OUT, respectively, and that form a Pch differential pair; Pch transistors P3, P4 whose sources are coupled to the power supply terminal and whose gates were coupled to each other; a Pch cascode current mirror (P3 to P6) that is comprised of the Pch transistors P5, P6 whose sources are coupled to drains of the Pch transistors P3, P4, respectively, whose gates are coupled to each other, and whose common gates are coupled to a drain of the Pch transistor P5, and such that a coupling point of the Pch transistors P3, P5 and a coupling point of the Pch transistors P4, P6 are coupled to drains of the Nch transistors N1, N2, respectively; Nch transistors N3, N4 whose sources are coupled to the GND terminal and whose gates were coupled to each other; a Nch cascode current mirror (N3 to N6) that is comprised of the Nch transistors N5, N6 whose sources are coupled to drains of the Nch transistors N3, N4, respectively, whose gates are coupled to each other, and such that common gates of the Nch transistors N3, N4 are coupled to a drain of the Nch transistor N5, and a coupling point of the Nch transistors N3, N5 and a coupling point of the Nch transistors N4, N6 are coupled to drains of the Pch transistors P1, P2, respectively; a communication circuit V1 (a voltage source) coupled between the drain of the Pch transistor P5 (an input node of the Pch cascode current mirror (P3 to P6)) and the drain of the Nch transistor N5 (an input node of the Nch cascode current mirror (N3 to N6); and a communication circuit V2 (a voltage source) coupled between a drain of the Pch transistor P6 (an output node of the Pch cascode current mirror (P3 to P6)) and a drain of the Nch transistor N6 (an output node of the Nch cascode current mirror (N3 to N6). As an output stage, the differential amplifier 700 has a Pch transistor P0 whose source is coupled to the power supply terminal, whose drain is coupled to an output terminal OUT, and whose gate is coupled to a coupling node of the output (a drain of P6) of the Pch cascode current mirror (P3 to P6) and the communication circuit V2, and an Nch transistor N0 whose source is coupled to the GND terminal, whose drain is coupled to the output terminal OUT, and whose gate is coupled to the coupling node of the output (the drain of N6) of the Nch cascode current mirror (N3 to N6) and the communication circuit V2. The differential amplifier 700 of FIG. 13 is a Rail-to-Rail differential amplifier capable of a voltage follower operation in an almost full range of voltages between the high-level power supply and the GND.
The slew rate boost circuit (SBC) 710 has: a current source IN11 whose one end is coupled to the GND terminal; Nch transistors N11, N12 whose sources are coupled to the other end of the current source IN11 in common, whose gates are coupled to the input terminal INP and the output terminal OUT, respectively, and that serve as an Nch differential pair; a current source IP11 whose one end is coupled to the power supply terminal; Pch transistors P11, P12 whose sources are coupled to the other end of the current source IN11 in common, whose gates are coupled to the input terminal INP and the output terminal OUT, respectively, and that serve as a Pch differential pair; Pch transistors P13, P14 that are coupled between drains (an output pair of the Nch differential pair) of the Nch transistors N11, N12 and the power supply terminal and receives a bias voltage VP1 at their gates; a Pch transistor P15 whose source is coupled to the power supply terminal and whose gate is coupled to gates of the Pch transistors P13, P14; a Pch transistor P16 whose source is coupled to a drain of the Pch transistor P15, whose gate is coupled to a coupling node of the drain of the Pch transistor P13 and the drain of the Nch transistor N11, and whose drain is coupled to a coupling node PI of the input node (drain of N5) of the Nch cascode current mirror and the communication circuit V1; Nch transistors N13, N14 that are coupled between drains (an output pair of the Pch differential pair) of the Pch transistors P11, P12 and the GND terminal, and receives a bias voltage VN1 at their gates; an Nch transistor N15 whose source is coupled to the GND terminal and whose gate is coupled to gates of the Nch transistors N13, N14; and an Nch transistor N16 whose source is coupled to a drain of the Nch transistor N15, whose gate is coupled to a coupling point of a drain of the Nch transistor N13 and a drain of the Pch transistor P11, and whose drain is coupled to a coupling node NI of the input node (the drain of P5) of the Pch cascode current mirror and the communication circuit V1.
The transistors P13, P14, and P15 that receive the bias voltage VP1 at their gates and the transistors N13, N14, and N15 that receive the bias voltage VN1 at their gates form respective current sources. The transistors P16, N16 form respective switches.
An action of the slew rate boost circuit (SBC) 710 will be explained below.
When the voltage of the input terminal INP becomes higher than the voltage of the output terminal OUT, drain currents of the Nch transistors N11, N12 that form the Nch differential pair of the slew rate boost circuit (SBC) 710 increase and decrease, respectively. Then, when a drain current of the Nch transistor N11 becomes larger than a current set by the Pch transistor P13, the potential of a coupling node of the Nch transistor N11 and the Pch transistor P13 falls. As a result, the Pch transistor P16 turns on, and the current set by the Pch transistor P15 is supplied to the node PI. This increases both the input currents (drain currents of N3 and N5) of the Nch cascode current mirror (N3 to N6) of the differential amplifier 700 and the output currents (drain currents of N4 and N6), and boosts reduction actions of the gate potentials of the output stage transistors P0 and N0.
Thus, addition of the action of the slew rate boost circuit (SBC) 710 to an amplifying action of the differential amplifier 700 boosts the charging operation of the output terminal OUT. Incidentally, when the voltage of the output terminal OUT approaches the voltage of the input terminal INP, the drain current of the Nch transistor N11 decreases, the Pch transistor P16 turns off, and current supply from the Pch transistor P15 to PI is stopped. The action of the slew rate boost circuit (SBC) 710 stops and a voltage variation of the output terminal OUT is caused only by the amplifying action of the differential amplifier 700.
Moreover, when the voltage of the input terminal INP becomes higher than the voltage of the output terminal OUT, drain currents (absolute values) of the Pch transistors P11, P12 that form the Pch differential pair of the slew rate boost circuit (SBC) 710 decrease and increase, respectively. However, since the coupling node of the Pch transistor P11 and the Nch transistor N13 receives a potential reducing action, the Nch transistor N16 is kept to be off and does not affect the amplifying action of the differential amplifier 700.
On the other hand, when the voltage of the input terminal INP becomes lower than the voltage of the output terminal OUT, the drain currents (absolute values) of the Pch transistors P11, P12 that form the Pch differential pair of the slew rate boost circuit (SBC) 710 increase and decrease, respectively.
Then, when the drain current (absolute value) of the Pch transistor P11 becomes larger than a current set by the Nch transistor N13, the Nch transistor N16 turns on, and the current set by the Nch transistor N15 is supplied to the node NI.
This increase both the input currents (drain currents (absolute values) of P3 and P5) of the Pch cascode current mirror of the differential amplifier 700 and the output currents (drain currents (absolute values) of P4 and P6), and boosts raising actions of the gate potentials of the output stage transistors P0, N0. Therefore, addition of the action of the slew rate boost circuit (SBC) 710 to the amplifying action of the differential amplifier 700 boosts the discharging operation of the output terminal OUT.
Incidentally, when the voltage of the output terminal OUT approaches the voltage of the input terminal INP, a drain current of the Pch transistor P11 decreases, the Nch transistor N16 turns off, and current supply from the Nch transistor N15 to the node NI is stopped. The action of the slew rate boost circuit (SBC) 710 stops and the voltage variation of the output terminal OUT is caused only by the amplifying action of the differential amplifier 700. Moreover, when the voltage of the input terminal INP becomes lower than the voltage of the output terminal OUT, drain currents (absolute values) of the Nch transistors N11, N12 that form the Nch differential pair of the slew rate boost circuit (SBC) 710 decrease and increase, respectively. However, at this time, the Pch transistor P16 is kept to be off (non-conduction), and does not affect the amplifying action of the differential amplifier 700.